ASIC/SoC DFT Engineer, Platforms @ Google - Sunnyvale, CA

Job Overview

2 months ago

ASIC/SoC DFT Engineer, Platforms

Google - Sunnyvale, CA

Minimum qualifications:

  • Bachelor's degree in Electrical/Computer Engineering, a related field, or equivalent practical experience
  • 7 years of experience in DFT specification, definition, insertion, and/or analysis in designs (e.g, CPU, GPU, etc.)
  • Experience in silicon bring-up, debug, and validation of DFT features on Automated Test Equipment (ATE)
  • Experience in fault modeling


Preferred qualifications:

  • Master's degree in Electrical or Computer Engineering
  • Experience in IP integration (e.g., memories, test controllers, test access point (TAP), and memory built-in self test (MBIST))
  • Experience Architecting chip-level DFT solutions
  • Experience using EDA test tools (e.g., Design Compiler, DFT Max, SpyGlass, Modus, Tessent, etc.)
  • Experience with and understanding of ASIC DFT, synthesis, simulation, and verification flow
  • Knowledge of various test standards and test formats

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

In this role, you will be responsible for defining, implementing, and deploying design-for-test (DFT) methodologies for complex digital and/or mixed-signal chips and/or IPs. This includes defining test strategies, DFT/DFD architecture, and creating DFT and debug specifications for next generation SoCs. You'll reduce test cost, increase production quality, and enhance yield.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

  • Develop DFT strategy and architecture, including arranging DFT/MBIST and ATPG.
  • Complete all test design checks and design changes to fix issues and achieve high test quality.
  • Insert DFT logic, including boundary scan, scan chains, DFT compression, logic BIST, TAP controller, clock control block, and other DFT IP blocks.
  • Insert and connect MBIST logic, including test collar around memories, MBIST controllers, and eFuse logic. Connect to core and TAP interfaces.
  • Document DFT architecture and test sequences, including boot-up sequence associated with test pins.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

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